1. Field of the Invention
The present invention relates to a SOI type semiconductor device using a bonded and etch-backed SOI substrate produced by selective polishing using a stopper, and a process of fabricating the same. In particular, the present invention relates to a SOIMOSFET having a structure such as a back gate electrode formed in a SOI substrate, and a process of fabricating the same.
2. Description of the Related Art
It has been known that a SOI (Silicon On Insulator) structure makes easy perfect isolation of elements and suppresses occurrence of a soft error and latch up inherent to a CMOSTr (Complementary Metal Oxide Semiconductor Transistor), and it has been relatively early examined to realize a high speed and high reliability CMOSTr-LSI by means of a SOI structure including a Si active layer having a thickness of about 500 nm.
In recent years, it has become apparent that the performances of the SOI structure can be more improved, for example, in terms of suppression of a short channel effect and enhancement of a current driving ability of the MOSTr by thinning a surface Si layer of the SOI structure to about 100 nm and controlling an impurity concentration in a channel at a relatively low value, thereby substantially depleting the entire Si active layer.
As a method for forming such a SOI layer, there has been known two relatively high level processes: a SIMOX (Separation by IMplanted OXygen) process and a wafer bonding process.
Each of these two processes, however, has a merit and a demerit at the present time. For example, a SOI substrate prepared by the SIMOX process is excellent in uniformity of thickness of a SOI film; however, it is poor in flatness at an interface with a buried oxide film, to degrade a reliability of a transistor. Besides, a SOI substrate prepared by the wafer bonding process is excellent in characteristic at an interface with a buried oxide film; however, it is particularly poor in uniformity of a thickness of a thin Si film.
Here, there will be briefly described steps of fabricating a SOI substrate in accordance with the wafer bonding process.
A SOI substrate is fabricated, in accordance with the wafer bonding process, by planarization-polishing and surface-treating a surface of an A substrate to be bonded, bonding a B substrate to the A substrate and annealing the bonded substrates A and B, and grinding and polishing the A substrate (selectively polishing, in the case of using a stopper). In the case of polishing the A substrate using a stopper, a-stepped-portion (which becomes a stopper layer) must be previously formed on the A substrate (which becomes the final SOI layer) before planarization-polishing the surface of the A substrate to be bonded.
The bonded and etch-backed wafer thus prepared is effective not only to relatively freely set a thickness of a buried oxide film and the like, but also to prepare a LSI in a state in which elements, interconnections, and the like are previously buried on the back side of the B substrate before bonding of the A substrate to the B substrate and hence to prepare a LSI of a higher degree of integration.
For example, in fabrication of a MOSFET, by burying a gate electrode (this is often called a back gate electrode) in a SOI substrate, it is possible not only to suppress a short channel effect and control a threshold voltage (Vth) and swing of a voltage in a transistor but also to apply the MOSFET to a X-MOS (a MOSTr allowing to simultaneously operate a front gate and a back gate, which is also called a xe2x80x9cDouble Gate MOSxe2x80x9d).
Incidentally, the related art process of fabricating a semiconductor device has the following problems. Now, there will be reviewed these problems along with description of the related art fabrication process.
FIG. 26A is a sectional view showing a process of fabricating a semiconductor device.
First, as shown in FIG. 26A, a photoresist film (not shown) is provided on a silicon substrate (A substrate) in a region in which a SOI layer 50 is to be formed. It should be noted that the positional relationship in the vertical direction shown in FIG. 26A is reversed to that in this description. The A substrate is anisotropically etched by RIE (Reactive Ion Etching) using the photoresist film as a mask, to form a stepped portion for forming the SOI layer 50 on the A substrate. In addition, the process of forming such a stepped portion is called a trench process (by anisotropic etching using RIE).
A back gate oxide film 53 is formed on the A substrate, and a back gate electrode 55 is formed on the back gate oxide film 53. On the back gate electrode 55 is deposited an interlayer insulating film (SOI2 film) 57 on which a poly-Si film (not shown) is formed. Then, the poly-Si film is planarized by polishing, and a supporting substrate (B substrate) 60 is bonded with the planarized surface of the poly-Si film.
The A substrate is polished from the back surface side using the back gate oxide film 53 as a stopper (this is called selective polishing), to prepare a semiconductor substrate (SOI substrate) having the SOI layer 50, in which the back gate electrode 55 is buried.
A sacrifice oxide film (not shown) is formed by sacrifice oxidation on the surface of the SOI layer 50 exposed by the above selective polishing. The sacrifice oxidation is performed to recover the surface state of the SOI layer 50 coarsened by selective polishing.
On both the sacrifice oxide film and the back gate oxide film 53 is provided a silicon nitride film (oxidation preventive film, not shown) positioned on the SOI active layer 50.
Next, by selectively oxidizing the back gate electrode 55 using the silicon nitride film (oxidation preventive film) as a mask, a thick oxide film 71 is formed on the back gate electrode 55. At this time, the back gate electrode 55 is oxidized through an oxide film grown from the back gate oxide film 53 by sacrifice oxidation. Then, both the silicon nitride film and the sacrifice oxide film are removed, to expose the surface of the SOI layer 50.
A front gate oxide film 61 is formed on the surface of the SOI layer 50, and a front gate electrode 75 is formed on both the front gate oxide film 61 and the thick oxide film 71. The step is followed by formation of a LDD (Lightly Doped Drain) region, a LDD-spacer (SOI2), and a diffusion layer.
Then, an interlayer insulating film 81 is formed on both the thick oxide film 71 and the front gate electrode 75. In both the interlayer dielectric film 81 and the thick oxide film 71 are formed contact holes in which tungsten (W) plugs 77 are buried. And, aluminum (Al) interconnections 79 are formed on both the W plugs 77 and the interlayer insulating film 81. In this state, one Al interconnection 79 is connected to the front gate electrode 75 through one W plug 77 and the other Al interconnection 79 is connected to the back gate electrode 55 through the other W plug 77.
The above-described fabrication process is characterized by forming the oxidation preventive mask on a portion of the SOI region and selectively oxidizing the back gate electrode 55, thereby making it possible to suppress a parasitic capacitance from being increased in the field area at a portion in which the front gate 75 is superimposed on the back gate electrode 55.
However, in the case where the back gate electrode 55 in the field area is entirely oxidized as described above, as shown in FIG. 26A, upon formation of the first contact, the connection hole in which the W plug 77 connected to the back gate electrode 55 is to be buried is required to be formed in such a manner as to be deeper in thickness corresponding to that of the thick oxide film 71 than the connection hole in which the W plug 77 connected to the front gate electrode 75 is to be buried. As a result, an aspect ratio of the contact hole reaching the back gate electrode 55 is increased, so that there may occur a void 77a in the W plug 77. This causes a problem that a contact resistance between the back gate electrode 55 and the W plug 77 at a portion 83 shown in FIG. 26A is increased.
FIG. 26B is a sectional view showing another process of fabricating a semiconductor device. In this figure, parts corresponding to those shown in FIG. 26A are indicated by the same reference numerals in FIG. 26A, and the explanation thereof is omitted. Hereinafter, there will be described only part of a configuration of this process different from that of the process shown in FIG. 26A.
In this process, the front gate electrode 75 does not cover a portion over the SOI layer 50, and a contact hole is provided in the interlayer dielectric film 81 at a position corresponding to that of the above portion over the SOI layer 50. The W plug 77 is formed in the connection hole. In this state, one Al interconnection 79 is connected to the SOI layer 50 through the W plug 77.
In the above-described process of fabricating a semiconductor device, when the contact hole in which the W plug 77 connected to the back gate electrode 55 is to be buried and the connection hole in which the W plug 77 connected to the SOI layer 50 is to be buried are simultaneously opened, there may occur a problem that the SOI layer 50 may be entirely etched off because of selectivity upon etching by RIE due to a difference in depth between the contact holes (see a portion 85 in FIG. 26B). This causes a problem of lowering a yield in burying the W plug 77 in the contact hole reaching the SOI layer 50. Additionally, since the contact hole in which the W plug 77 connected to the back gate electrode 55 is to be buried is required to be formed in such a manner as to be deeper by the thickness corresponding to that of the thick oxide film 71 than the contact hole connected to the SOI layer 50 is to be buried, there may occur a void 77a in the W plug 77.
Accordingly, there has been strong demands to develop a fabrication process capable of suppressing a parasitic capacitance from being increased in the field area at a portion between the front gate electrode 75 and the back gate electrode 55 by selectively oxidizing the back gate electrode 55 in the field area while preventing an increase in an aspect ratio of a contact hole reaching the back gate electrode 55.
FIG. 27A is a sectional view of a semiconductor device fabricated by a process similar to that shown in FIG. 26A, illustrating another problem; and FIG. 27B is a sectional view of a semiconductor device fabricated by a process similar to that shown in FIG. 26B, illustrating another problem. In these figures, parts corresponding to those shown in FIGS. 26A and 26B are indicated by the same reference numerals as those in FIGS. 26A and 26B.
As shown in FIGS. 27A and 27B, in the case where the back gate electrode 55 formed of the poly-Si film having a thickness of less than 300 nm is oxidized from the front surface side for forming the thick oxide film 71, the back gate electrode 55 in which grains of poly-Si have been grown at high temperatures through wafer bonding process is oxidized, and accordingly, oxidation of the back gate electrode 55 abnormally proceeds along grain boundaries of poly-Si. For example, in the case where the poly-Si film (back gate electrode 55) having the initial thickness of less than 300 nm is oxidized a thickness of less than 200 nm to form the oxide film 71 having a thickness of less than 400 nm for suppressing a parasitic capacitance in the field area at a portion between the front gate electrode 75 and the back gate electrode 55, the remaining thickness of the poly-Si film becomes less than 100 nm. At this time, if the poly-Si film is abnormally oxidized along grain boundaries, the remaining thickness of the poly-Si film is very thinned (see a portion 101 in FIG. 27A), with a result that a local sheet resistance may be finally increased. In the worst case, as oxidation of the back gate electrode 55 further proceeds, there may occur an inconvenience that the poly-Si film (back gate electrode 55) may be disconnected (see a portion 103 in FIG. 27B).
In the case where the back gate electrode 55 is made from p+ poly-Si doped with boron (B), since boron as a dopant is precipitated at an interface between the poly-Si film 55 and the oxide film (SOI2 film) 71 during oxidation of the back gate electrode 55, a final sheet resistance Rs of the back gate electrode 55 is increased more than that of the thinned poly-Si film.
In view of the foregoing, there have been strong demands to provide a semiconductor device capable of suppressing a parasitic capacitance from being increased in a field area at a portion between a front gate electrode 75 and a back gate electrode 55 by selectively oxidizing the back gate electrode 55 in the field area and also capable of suppressing a disconnection or an increase in sheet resistance of the back gate electrode 55 in the field area, and to provide a process of fabricating the semiconductor device.
An object of the present invention is to provide a semiconductor device capable of forming a contact reaching a back gate electrode without increasing an aspect ratio of the contact even if a thick oxide film is grown on the back gate electrode in a field area by selectively oxidizing the back gate electrode in the field area, and a process of fabricating the semiconductor device.
Another object of the present invention is to provide a semiconductor device capable of suppressing a disconnection or an increase in sheet resistance of a back gate electrode or structure even if a thick oxide film is grown on the back gate electrode or structure in a field area by selectively oxidizing the back gate electrode or structure in the field area, and a process of fabricating the semiconductor device.
To achieve the above objects, according to the present invention, there is provided a semiconductor device of a SOI type in which a structure made from a semiconductor material is buried, including: an oxide film selectively grown on the structure except for a partial region of the structure.
According to the present invention, there is also provided a semiconductor device including: a SOI substrate having a SOI layer, in which a structure made from a semiconductor material is buried; a thick oxide film formed on the structure by selectively oxidizing the structure using as a mask an oxidation preventive film formed both on the SOI layer and on a region in which a contact reaching the structure is to be formed; an interlayer dielectric film formed on the structure, the SOI layer and the thick oxide film; and a plurality of connection holes formed in the interlayer insulating film and including at least a connection hole positioned on the region in which the contact is to be formed.
In the semiconductor device of the present invention, when a thick oxide film is formed on a structure except for a partial region of the structure, an oxidation preventive mask is formed not only on a SOI active region but also on a portion in which a contact reaching the structure is to be formed for preventing oxidation of such a portion as well as the SOI active region. As a result, even when the thick oxide film is grown on the structure in the field area, the portion in which the contact is to be formed is substantially at the same level of the SOI layer, so that it is possible to prevent an increase in an aspect ratio of a connection hole.